SCM system will appear in the interference of the outside world, the phenomenon of running out of the program to cause an endless loop, watchdog circuit is to avoid this happening. The role of the watchdog is to enable the processor to automatically reset (reset the reset signal) by not receiving the dog feed signal (indicating that the MCU is already hung) for a certain period of time (via the timer counter).
The STM32's independent watchdog is driven by an internal 40Khz low-speed clock, which is still valid even if the master clock fails. It should be noted here that the clock of the independent watchdog is an internal RC clock, so it is not an accurate 40Khz, but a variable clock between 30~60Khz. It is only at the time of estimation that we calculate at 40Khz. The watchdog's time requirement is not very accurate. Therefore, the clock is somewhat biased and acceptable.
The registers involved are: key register IWDG_KR, prescaler IWDG_PR, reload register IWDG_RLR, status register | IWDG_SR.
Functional description:
Write 0xCCCC in the key value register (IWDG_KR) to start the independent watchdog; the counter starts to count down from its reset value 0xFFF. When the counter reaches the end of 0x000, a reset signal (IWDG_RESET) is generated. Whenever 0xAAAA is written in the key register IWDG_KR, the value in IWDG_RLR is reloaded into the counter to avoid a watchdog reset.
The IWDG_PR and IWDG_RLR registers are write-protected. To modify the values ​​of these two registers, you must first write 0x5555 to the IWDG_KR register. Writing other values ​​to this register will disrupt the operation sequence and the registers will be protected again. The reload operation (ie write 0xAAAA) also initiates write protection.
There are also two registers, a prescaler register (IWDG_PR), which is used to set the division factor of the watchdog clock. Another reload register. This register is used to hold the value reloaded into the counter. This register is also a 32-bit register, but only the lower 12 bits are valid.
Configuration steps:
1) Cancel register write protection (write 0x5555 to IWDG_KR)
2) Set the independent watchdog prescaler and reload value
3) Feed the dog with the reload count (write 0XAAAA to IWDG_KR)
4) Start watchdog (write 0XCCCC to IWDG_KR)
STM32 independent watchdog programThe IWDG is best suited for applications that require the watchdog to be able to work completely independently of the main program and require less time accuracy.
/************************************************* ******************************
*
* Software function: Independent watchdog experiment
*
************************************************** *****************************/
#include "stm32f10x.h"
#include "delay.h"
/*************************************************
Function: void RCC_ConfiguraTIon(void)
Function: Configure the system clock
Parameters: None
Return: None
************************************************** /
Void RCC_ConfiguraTIon(void)
{
ErrorStatus HSEStartUpStatus; //define external high-speed crystal startup status enumeration variable
RCC_DeInit(); //Reset RCC external device register to default value
RCC_HSEConfig(RCC_HSE_ON); //Open external high-speed crystal
HSEStartUpStatus = RCC_WaitForHSEStartUp(); // Wait for external high-speed clock ready
If(HSEStartUpStatus == SUCCESS) //The external high-speed clock has been accurate
{
FLASH_PrefetchBufferCmd (FLASH_PrefetchBuffer_Enable); //Open the FLASH read-ahead buffer function to speed up the reading of FLASH. Required for all programs. Location: Inside the RCC initialization subfunction, after the clock has started
FLASH_SetLatency (FLASH_Latency_2); //flash operation delay
RCC_HCLKConfig(RCC_SYSCLK_Div1); //Configure AHB(HCLK) clock equal to==SYSCLK
RCC_PCLK2Config(RCC_HCLK_Div1); //Configure APB2(PCLK2) clock==AHB clock
RCC_PCLK1Config(RCC_HCLK_Div2); //Configure APB1(PCLK1) clock==AHB1/2 clock
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); //Configure PLL Clock == External High-Speed ​​Crystal Clock* 9 = 72MHz
RCC_PLLCmd(ENABLE); //Enable PLL clock
While(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) //wait for PLL clock ready
{
}
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //Configure system clock = PLL clock
While(RCC_GetSYSCLKSource() != 0x08) //Check if the PLL clock is used as the system clock
{
}
}
}
/************************************************* *********************
* Name: GPIO_ConfiguraTIon()
* Function: Configure input and output
* Entry parameters:
* Export parameters:
-------------------------------------------------- ---------------------
* Description: Use library functions to configure the IO port
************************************************** *********************/
Void GPIO_ConfiguraTIon(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB , ENABLE); //clock to GPIOB
/*Set PB0 to output*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_10MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOB, & GPIO_InitStructure);
}
/************************************************* *********************
* Name: IWDG_Configuration()
* Function: watchdog configuration
* Entry parameters:
* Export parameters:
************************************************** *********************/
Void IWDG_Configuration(void)
{
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); // first enable register write before access
IWDG_SetPrescaler(IWDG_Prescaler_64); //The internal low-speed clock is divided by 16, ie the frequency is: 40K/64 = 0.625K, so one cycle is: 1.6ms
IWDG_SetReload(800); //800*1.6ms = 1.28S
IWDG_ReloadCounter(); //feed the dog program. Software must write 0xAAAA at certain intervals. Otherwise, the watchdog will generate a reset when the counter is 0.
IWDG_Enable(); //Enable
}
/************************************************* *********************
* Name: main()
* Function: Main function
* Entry parameters:
* Export parameters:
************************************************** *********************/
Int main (void)
{
RCC_Configuration(); //Configure the clock
GPIO_Configuration(); //Configure IO port
IWDG_Configuration(); //Configure Watchdog
Delay_init(72);
GPIO_SetBits(GPIOB, GPIO_Pin_0);
Delay_ms(300);
GPIO_ResetBits(GPIOB, GPIO_Pin_0);
While(1)
{
Delay_ms(10);
//IWDG_ReloadCounter(); //feed the dog program. Software must write 0xAAAA at certain intervals. Otherwise, the watchdog will generate a reset when the counter is 0. This line should be removed during normal use.
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