The semiconductor research company established by the University of California, Los Angeles (UCLA) recently proposed a new chip process screening technology, which is said to reduce chip production costs by 15% and increase the profit per chip by up to 12%.
Currently, this new screening technology is being characterized by IBM on its 45nm process using an on-wafer monitoring structure that can initially stop producing problematic wafers.
Wafer screening technology can locate test structures between grains on a wafer, similar to today's test structures used to monitor process drift. By reusing these test architectures to screen wafers, problematic wafers can be screened early in the production process by detecting errors in the test structure, thereby improving the overall yield and final revenue.
"Wafer screening technology is expected to enable lower-cost, higher-performance electronic devices, especially if they can be screened early in the process," said Puneet Gupta, a SRC alumnus and professor of electrical engineering at UCLA. "Especially in the early stages of production, screening technology is very useful for improving chip yield."
Design-dependent processes monitor failure points on wafers early in production by comparing the designer's timing and power models with measurements from specific test structures between die.
This design-dependent process is primarily a matter of installing a very easy-to-test structure that detects abnormal capacitance, resistance, and other minor signs that may indicate possible damage to neighboring die. If enough error information can be detected early in wafer production, then it is no longer necessary to continue manufacturing the wafer. By screening failed wafers, the cost of additional process steps that may occur, such as complex metal layers, can be significantly reduced.
Gupta estimates that using this test structure to perform a wide range of power level and performance change detection, approximately 70% of failed chips can be screened. The simple test structure positioned between the die can determine the precise inspection position at the early stage of manufacturing before cutting and packaging, thereby reducing the cost of failure detection testing of the finished chip.
"As a result of design-assisted manufacturing technologies developed by Prof. Gupta, we can fully utilize design information to reduce process control requirements. All of our members can benefit from this," said Bill Joyner, director of computer assistive device design and testing at SRC. "Designing auxiliary manufacturing also contributes to our technological progress."
IBM will test the wafer screening technology developed by Prof. Gupta by adding the necessary test structures to its 45-nm process, and will perform necessary tests during production to screen out possible wafer failures. By carefully tracking all the indicators, IBM hopes to analyze the yield improvement and cost savings that the technology can achieve. Once the actual test is completed, the wafer screening process can be used by all SRC member companies including AMD, Freescale, Globalfoundries, IBM, Intel and Texas Instruments.
Currently, this new screening technology is being characterized by IBM on its 45nm process using an on-wafer monitoring structure that can initially stop producing problematic wafers.
Wafer screening technology can locate test structures between grains on a wafer, similar to today's test structures used to monitor process drift. By reusing these test architectures to screen wafers, problematic wafers can be screened early in the production process by detecting errors in the test structure, thereby improving the overall yield and final revenue.
"Wafer screening technology is expected to enable lower-cost, higher-performance electronic devices, especially if they can be screened early in the process," said Puneet Gupta, a SRC alumnus and professor of electrical engineering at UCLA. "Especially in the early stages of production, screening technology is very useful for improving chip yield."
Design-dependent processes monitor failure points on wafers early in production by comparing the designer's timing and power models with measurements from specific test structures between die.
This design-dependent process is primarily a matter of installing a very easy-to-test structure that detects abnormal capacitance, resistance, and other minor signs that may indicate possible damage to neighboring die. If enough error information can be detected early in wafer production, then it is no longer necessary to continue manufacturing the wafer. By screening failed wafers, the cost of additional process steps that may occur, such as complex metal layers, can be significantly reduced.
Gupta estimates that using this test structure to perform a wide range of power level and performance change detection, approximately 70% of failed chips can be screened. The simple test structure positioned between the die can determine the precise inspection position at the early stage of manufacturing before cutting and packaging, thereby reducing the cost of failure detection testing of the finished chip.
"As a result of design-assisted manufacturing technologies developed by Prof. Gupta, we can fully utilize design information to reduce process control requirements. All of our members can benefit from this," said Bill Joyner, director of computer assistive device design and testing at SRC. "Designing auxiliary manufacturing also contributes to our technological progress."
IBM will test the wafer screening technology developed by Prof. Gupta by adding the necessary test structures to its 45-nm process, and will perform necessary tests during production to screen out possible wafer failures. By carefully tracking all the indicators, IBM hopes to analyze the yield improvement and cost savings that the technology can achieve. Once the actual test is completed, the wafer screening process can be used by all SRC member companies including AMD, Freescale, Globalfoundries, IBM, Intel and Texas Instruments.
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