All Commandline can be found in ISE's help->User Manuals, in User Manuals
XST User Guide ------- The command on XST is separate in this document;
Command line tools user guide ---------ngdbuild, PAR, map, trce, bitgen, etc. are all here
Here are all reposts:
Because a project currently in use uses multiple Xilinx FPGAs with large capacity, the synthesis, map, P&R, and generaTIng programming files for each FPGA become a big problem. (Hey, no one in the group has the experience of modular design.) Although the performance of today's workstations is relatively strong, it still takes several hours to generate each programming file. So considering all the compilation work under Command Line, here's a little bit of it, I hope to help everyone.
To complete a complete Xilinx FPGA compilation process, the Command involved includes:
XST:
Fully known as Xilinx Synthesis Technology, this is a free comprehensive tool included with Xilinx ISE. (Oh, the purchase of Synplify Pro is being negotiated.) After the Synthesis is completed, you can use any text tool to open the file with the suffix ".syr" to see the specific operation process and report of the synthesis.
NGDBuild:
This order is actually a translate. This is the first step of implementaTIon. It will merge all the netlists and design constraints together to generate an ngd file for use by the map tool. Similarly, the NGDBuild report file is a file with the suffix ".bld".
MAP:
The MAP command maps the ngd file generated by the NGDBuild command to a specific FPGA device. MAP will generate an NCD file for use by the PAR. You can use any text tool to open a map report file with the suffix ".mrp".
PAR:
Place & Route. This is not even more to say. Avoid being caught by bricks. The PAR report file suffix is ​​".par".
TRCE:
This is used to generate the TIming report that we are most concerned about. TRCE analyzes the design of your FPGA and produces a timing report with the suffix ".twr". You can open it with any text tool, or you can use xilinx's TIming Analyzer. The Timing Analyzer is intuitive and recommended for beginners.
Bitgen:
As the name suggests, this Bitgen is used to generate programming files.
After introducing the commands provided by Xilinx, let's take a look at how to use them. Xilinx gives us a useful tool: View Command Line Log File. This tool is located under Design Entry Utitlities in the Process for Source window.
Double click on this View Command Line Log File, what do you see? Haha, a statement similar to the following appears in the text editing window on the right:
Xst -intstyle ise -ifn __projnav/fpga_a.xst -ofn fpga_a.syr
Ngdbuild -intstyle ise -dd d:\projects\hardware\hy_multifpga_nwpci_vhd_new_improvetiming/_ngo -uc ./source/hy/fpga_a.ucf -aul -p xc2v6000-ff1152-4 fpga_a.ngc fpga_a.ngd
Map -intstyle ise -p xc2v6000-ff1152-4 -cm area -pr b -k 4 -c 100 -tx off -o fpga_a_map.ncd fpga_a.ngd fpga_a.pcf
Par -w -intstyle ise -ol high -t 1 fpga_a_map.ncd fpga_a.ncd fpga_a.pcf
Trce -intstyle ise -e 1000 -l 1000 -xml fpga_a fpga_a.ncd -o fpga_a.twr fpga_a.pcf
Bitgen -intstyle ise -f fpga_a.ut fpga_a.ncd
By the way, these are the commands you have used before. In fact, when we use ISE for Synthesis, Map, PAR, ISE will automatically call the commands mentioned above, ISE is actually a GUI. :-)
If you double-click View Command Line Log File, the following error message appears:
Warning: This process is used to display the running command log file that records some application command lines.
This means that you have not implemented your design, or you have emptied the design. (Under the project directory, there is a cleanup project files button that can be cleared)
Next, it is the last step. You only need to use any text editor to save the history and copy of the above Command as a ".Bat" batch file, and execute it under the command line of windows. Note that you need to put this .bat file in the directory where your project is located.
a. If you want to run several projects in succession, it is recommended to use Cleanup Project Files first. According to the experience of the couple, Synthesis and PAR sometimes make mistakes if you do not clear them. However, there will be a small problem here. After the emptying, some original files may be deleted, such as *.xst under the __projnav directory (this time XST configuration file, when doing Synthesis, XST will read this file to get Related configuration), such as *.prj (project file, which lists some of the modules used by your design) and *.ut files (ut is Bitgen's configuration file). These three files, it is best to confirm the existence of the Command Line before using it. I usually put these 3 kinds of files back up, and when I get it, I will use it.
b. Under the Xilinx installation directory Xilinx\doc\usenglish\books\docs, there are pdf files for these commands, which can be read if needed. However, after a while, after reading it for a while, I found out that it was not really necessary. Let me have a problem.
In fact, this topic is relatively simple, and it can be said clearly in a few words. However, according to the novice experience of the past, I believe that it is better to explain some things in more detail. At least let the novices know more about ISE itself.
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